METASymbiose is a small company with skills and a long experience in the field of ASIC Design/Verification and therefore capable of offering a wide range of services ranging from a one-off intervention to the setup of a team to carry out an entire ASIC design/verification project. Topics likely to be covered by us are:

. Proof of concept (e.g., performance evaluation using Petri Net, Network Calculus)

. Architecture Design and Validation (e.g., Transaction-Level Modelling and Validation)

. RTL Design and Verification (Vhdl/SystemVerilog Modelling, Synthesis, Simulation, Sanity Checking, Model Checking)

. Hardware Emulation (e.g., using MG/Veloce™) and/or FPGA-based Prototyping.

METASymbiose has also developed a rich portfolio of specific/generic CAD tools whose general-purpose tools combine to form the backbone of an ASIC verification methodology including LogAbs for the abstraction of transistor networks, LogEq for the Formal Equivalence Checking at logic/gate level and LogCheck for Model Checking supporting both LTL and CTL.

More recently, METASymbiose is moving into the field of AI and offers services on the implementation and management of AI environments (e.g., interaction of ML/DL frameworks with hardware and/or software accelerators) as well as the development, [distributed/federated] training and [hardware/software-accelerated] exploitation of ANN models. The work even goes beyond classic ML/DL to address the simulation/emulation of neuromorphic computing.